/* 
* This file is part of STiD135 OXFORD LLA 
* 
* Copyright (c) <2014>-<2018>, STMicroelectronics - All Rights Reserved 
* Author(s): Mathias Hilaire (mathias.hilaire@st.com), Thierry Delahaye (thierry.delahaye@st.com) for STMicroelectronics. 
* 
* License terms: BSD 3-clause "New" or "Revised" License. 
* 
* Redistribution and use in source and binary forms, with or without 
* modification, are permitted provided that the following conditions are met: 
* 
* 1. Redistributions of source code must retain the above copyright notice, this 
* list of conditions and the following disclaimer. 
* 
* 2. Redistributions in binary form must reproduce the above copyright notice, 
* this list of conditions and the following disclaimer in the documentation 
* and/or other materials provided with the distribution. 
* 
* 3. Neither the name of the copyright holder nor the names of its contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
* 
*/ 
#ifndef _DVBSX_AGCRF_REG_INIT_H
#define _DVBSX_AGCRF_REG_INIT_H

/* -------------------------------------------------------------------------
 * File name  : dvbsx_agcrf_reg_init.h
 * File type  : C header file
 * -------------------------------------------------------------------------
 * Description:  Register map constants
 * Generated by spirit2regtest v2.24_alpha3
 * -------------------------------------------------------------------------
 */


/* Register map constants */

/* AGCRFCFG */
#define RC8CODEW_DVBSX_AGCRF_AGCRFCFG                                0x00000000
#define RC8CODEW_DVBSX_AGCRF_AGCRFCFG__DEFAULT                       0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRFCFG_AGCRF_BETA__MASK               0x0F      
#define FC8CODEW_DVBSX_AGCRF_AGCRFCFG_AGCRF_OVADC_DETECT__MASK       0x10      
#define FC8CODEW_DVBSX_AGCRF_AGCRFCFG_AGCRF_DC_CTRL__MASK            0xC0      

/* AGCRFRFN */
#define RC8CODEW_DVBSX_AGCRF_AGCRFRFN                                0x00000001
#define RC8CODEW_DVBSX_AGCRF_AGCRFRFN__DEFAULT                       0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRFRFN_AGCRF_INFLIMIT__MASK           0x0F      
#define FC8CODEW_DVBSX_AGCRF_AGCRFRFN_AGCRF_SUPLIMIT__MASK           0xF0      

/* AGCRFCN */
#define RC8CODEW_DVBSX_AGCRF_AGCRFCN                                 0x00000002
#define RC8CODEW_DVBSX_AGCRF_AGCRFCN__DEFAULT                        0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRFCN_RST_AGCRF__MASK                 0x06      
#define FC8CODEW_DVBSX_AGCRF_AGCRFCN_DIS_AGCRF_CTRL__MASK            0x08      
#define FC8CODEW_DVBSX_AGCRF_AGCRFCN_AGCRF_MINPOWER__MASK            0x10      
#define FC8CODEW_DVBSX_AGCRF_AGCRFCN_AGCRF_NOSLOWLK__MASK            0x20      
#define FC8CODEW_DVBSX_AGCRF_AGCRFCN_AGCRF_NOSIGNAL__MASK            0x40      
#define FC8CODEW_DVBSX_AGCRF_AGCRFCN_AGCRF_LOCKED__MASK              0x80      

/* AGCRFREF */
#define RC8CODEW_DVBSX_AGCRF_AGCRFREF                                0x00000003
#define RC8CODEW_DVBSX_AGCRF_AGCRFREF__DEFAULT                       0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRFREF_AGCRF_REF__MASK                0xFF      

/* IQDC_AGCCFG */
#define RC8CODEW_DVBSX_AGCRF_IQDC_AGCCFG                             0x00000004
#define RC8CODEW_DVBSX_AGCRF_IQDC_AGCCFG__DEFAULT                    0x0       
#define FC8CODEW_DVBSX_AGCRF_IQDC_AGCCFG_DCCOMP_BETA__MASK           0x07      
#define FC8CODEW_DVBSX_AGCRF_IQDC_AGCCFG_AGC_PWM_SPEED__MASK         0x70      
#define FC8CODEW_DVBSX_AGCRF_IQDC_AGCCFG_AGCRFBB_PWM_SWAP__MASK      0x80      

/* IQDCCOMPCFG */
#define RC8CODEW_DVBSX_AGCRF_IQDCCOMPCFG                             0x00000005
#define RC8CODEW_DVBSX_AGCRF_IQDCCOMPCFG__DEFAULT                    0x0       
#define FC8CODEW_DVBSX_AGCRF_IQDCCOMPCFG_AGCRF_I2CCONSTEL_LIGNE__MASK 0x0F      
#define FC8CODEW_DVBSX_AGCRF_IQDCCOMPCFG_AGCRF_IDCCOMP_OV__MASK      0x10      
#define FC8CODEW_DVBSX_AGCRF_IQDCCOMPCFG_AGCRF_QDCCOMP_OV__MASK      0x20      

/* AGCRF_IDCCOMP */
#define RC8CODEW_DVBSX_AGCRF_AGCRF_IDCCOMP                           0x00000006
#define RC8CODEW_DVBSX_AGCRF_AGCRF_IDCCOMP__DEFAULT                  0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRF_IDCCOMP_AGCRF_IAVERAGE_ADJ__MASK  0xFF      

/* AGCRF_IDCCOMP2 */
#define RC8CODEW_DVBSX_AGCRF_AGCRF_IDCCOMP2                          0x00000007
#define RC8CODEW_DVBSX_AGCRF_AGCRF_IDCCOMP2__DEFAULT                 0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRF_IDCCOMP2_AGCRF_OVADCI__MASK       0xFF      

/* AGCRF_QDCCOMP */
#define RC8CODEW_DVBSX_AGCRF_AGCRF_QDCCOMP                           0x00000008
#define RC8CODEW_DVBSX_AGCRF_AGCRF_QDCCOMP__DEFAULT                  0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRF_QDCCOMP_AGCRF_QAVERAGE_ADJ__MASK  0xFF      

/* AGCRF_QDCCOMP2 */
#define RC8CODEW_DVBSX_AGCRF_AGCRF_QDCCOMP2                          0x00000009
#define RC8CODEW_DVBSX_AGCRF_AGCRF_QDCCOMP2__DEFAULT                 0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRF_QDCCOMP2_AGCRF_OVADCQ__MASK       0xFF      

/* AGCRF_POWERI */
#define RC8CODEW_DVBSX_AGCRF_AGCRF_POWERI                            0x0000000a
#define RC8CODEW_DVBSX_AGCRF_AGCRF_POWERI__DEFAULT                   0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRF_POWERI_AGCRF_POWER_I__MASK        0xFF      

/* AGCRF_POWERQ */
#define RC8CODEW_DVBSX_AGCRF_AGCRF_POWERQ                            0x0000000b
#define RC8CODEW_DVBSX_AGCRF_AGCRF_POWERQ__DEFAULT                   0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRF_POWERQ_AGCRF_POWER_Q__MASK        0xFF      

/* AGCRFIN1 */
#define RC8CODEW_DVBSX_AGCRF_AGCRFIN1                                0x0000000c
#define RC8CODEW_DVBSX_AGCRF_AGCRFIN1__DEFAULT                       0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRFIN1_AGCRF_VALUE__MASK              0xFF      

/* AGCRFIN0 */
#define RC8CODEW_DVBSX_AGCRF_AGCRFIN0                                0x0000000d
#define RC8CODEW_DVBSX_AGCRF_AGCRFIN0__DEFAULT                       0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRFIN0_AGCRF_VALUE__MASK              0xFF      

/* AGCINC */
#define RC8CODEW_DVBSX_AGCRF_AGCINC                                  0x0000000e
#define RC8CODEW_DVBSX_AGCRF_AGCINC__DEFAULT                         0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCINC_AGC_REF_MSB__MASK                0x3F      
#define FC8CODEW_DVBSX_AGCRF_AGCINC_PWM_RF_INV__MASK                 0x40      
#define FC8CODEW_DVBSX_AGCRF_AGCINC_PWM_BB_INV__MASK                 0x80      

/* AGCRF_TESTBUS */
#define RC8CODEW_DVBSX_AGCRF_AGCRF_TESTBUS                           0x0000000f
#define RC8CODEW_DVBSX_AGCRF_AGCRF_TESTBUS__DEFAULT                  0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRF_TESTBUS_TAG2CBUS__MASK            0x3F      

/* AGCRF_PWMRFINC */
#define RC8CODEW_DVBSX_AGCRF_AGCRF_PWMRFINC                          0x00000010
#define RC8CODEW_DVBSX_AGCRF_AGCRF_PWMRFINC__DEFAULT                 0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRF_PWMRFINC_PWM_RF_INC__MASK         0xFF      

/* AGCRF_PWMBBINC */
#define RC8CODEW_DVBSX_AGCRF_AGCRF_PWMBBINC                          0x00000011
#define RC8CODEW_DVBSX_AGCRF_AGCRF_PWMBBINC__DEFAULT                 0x0       
#define FC8CODEW_DVBSX_AGCRF_AGCRF_PWMBBINC_PWM_BB_INC__MASK         0xFF      


/* Number of registers */
#define C8CODEW_DVBSX_AGCRF_REG_NBREGS                               18        

/* Number of fields */
#define C8CODEW_DVBSX_AGCRF_REG_NBFIELDS                             32        



#endif /* #ifndef _DVBSX_AGCRF_REG_INIT_H */
