/* 
* This file is part of STiD135 OXFORD LLA 
* 
* Copyright (c) <2014>-<2018>, STMicroelectronics - All Rights Reserved 
* Author(s): Mathias Hilaire (mathias.hilaire@st.com), Thierry Delahaye (thierry.delahaye@st.com) for STMicroelectronics. 
* 
* License terms: BSD 3-clause "New" or "Revised" License. 
* 
* Redistribution and use in source and binary forms, with or without 
* modification, are permitted provided that the following conditions are met: 
* 
* 1. Redistributions of source code must retain the above copyright notice, this 
* list of conditions and the following disclaimer. 
* 
* 2. Redistributions in binary form must reproduce the above copyright notice, 
* this list of conditions and the following disclaimer in the documentation 
* and/or other materials provided with the distribution. 
* 
* 3. Neither the name of the copyright holder nor the names of its contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
* 
*/ 
#ifndef _C8CODEW_TOP_CTRL_REG_INIT_H
#define _C8CODEW_TOP_CTRL_REG_INIT_H

/* -------------------------------------------------------------------------
 * File name  : c8codew_top_ctrl_reg_init.h
 * File type  : C header file
 * -------------------------------------------------------------------------
 * Description:  Register map constants
 * Generated by spirit2regtest v2.24_alpha3
 * -------------------------------------------------------------------------
 */


/* Register map constants */

/* MID */
#define RC8CODEW_C8CODEW_TOP_CTRL_MID                                0x00000000
#define RC8CODEW_C8CODEW_TOP_CTRL_MID__DEFAULT                       0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_MID_MRELEASE__MASK                 0x0F      
#define FC8CODEW_C8CODEW_TOP_CTRL_MID_MCHIP_IDENT__MASK              0xF0      

/* DID */
#define RC8CODEW_C8CODEW_TOP_CTRL_DID                                0x00000001
#define RC8CODEW_C8CODEW_TOP_CTRL_DID__DEFAULT                       0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_DID_DEVICE_ID__MASK                0xFF      

/* TOP_FRES */
#define RC8CODEW_C8CODEW_TOP_CTRL_TOP_FRES                           0x00000010
#define RC8CODEW_C8CODEW_TOP_CTRL_TOP_FRES__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_TOP_FRES_TOP_FRESINT__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_TOP_FRES_TOP_FRESMAS__MASK         0x02      
#define FC8CODEW_C8CODEW_TOP_CTRL_TOP_FRES_TOP_FRESI2C__MASK         0x04      
#define FC8CODEW_C8CODEW_TOP_CTRL_TOP_FRES_FRESTUNER__MASK           0x78      
#define FC8CODEW_C8CODEW_TOP_CTRL_TOP_FRES_FRESFEC__MASK             0x80      

/* TOP_STOPCLK */
#define RC8CODEW_C8CODEW_TOP_CTRL_TOP_STOPCLK                        0x00000011
#define RC8CODEW_C8CODEW_TOP_CTRL_TOP_STOPCLK__DEFAULT               0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_TOP_STOPCLK_STOP_CKTUNER__MASK     0x0F      

/* ADCICFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_ADCICFG                            0x00000020
#define RC8CODEW_C8CODEW_TOP_CTRL_ADCICFG__DEFAULT                   0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICFG_ADCI1_SIGN__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICFG_ADCI1_REVERSE__MASK        0x02      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICFG_ADCI2_SIGN__MASK           0x04      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICFG_ADCI2_REVERSE__MASK        0x08      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICFG_ADCI3_SIGN__MASK           0x10      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICFG_ADCI3_REVERSE__MASK        0x20      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICFG_ADCI4_SIGN__MASK           0x40      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICFG_ADCI4_REVERSE__MASK        0x80      

/* DSQADCICFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_DSQADCICFG                         0x00000021
#define RC8CODEW_C8CODEW_TOP_CTRL_DSQADCICFG__DEFAULT                0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_DSQADCICFG_DISEQC_ADCI_SIGN__MASK  0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_DSQADCICFG_DISEQC_ADCI_GAIN__MASK  0x02      

/* ADCICLK */
#define RC8CODEW_C8CODEW_TOP_CTRL_ADCICLK                            0x00000022
#define RC8CODEW_C8CODEW_TOP_CTRL_ADCICLK__DEFAULT                   0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICLK_ADCI1_INVCLK__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICLK_ADCI2_INVCLK__MASK         0x02      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICLK_ADCI3_INVCLK__MASK         0x04      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICLK_ADCI4_INVCLK__MASK         0x08      
#define FC8CODEW_C8CODEW_TOP_CTRL_ADCICLK_I2C_FSKI_INVCLK__MASK      0x80      

/* SYNTCTRL */
#define RC8CODEW_C8CODEW_TOP_CTRL_SYNTCTRL                           0x00000030
#define RC8CODEW_C8CODEW_TOP_CTRL_SYNTCTRL__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_SYNTCTRL_STANDBY__MASK             0x80      

/* I2CCFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CCFG                             0x00000031
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CCFG__DEFAULT                    0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CCFG_STATUS_WR__MASK             0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CCFG_I2C_FORCEACT__MASK          0x02      

/* SYSSTATUS1 */
#define RC8CODEW_C8CODEW_TOP_CTRL_SYSSTATUS1                         0x00000032
#define RC8CODEW_C8CODEW_TOP_CTRL_SYSSTATUS1__DEFAULT                0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_SYSSTATUS1_CHIP_SYSSTATUS__MASK    0xFF      

/* SYSSTATUS0 */
#define RC8CODEW_C8CODEW_TOP_CTRL_SYSSTATUS0                         0x00000033
#define RC8CODEW_C8CODEW_TOP_CTRL_SYSSTATUS0__DEFAULT                0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_SYSSTATUS0_CHIP_SYSSTATUS__MASK    0xFF      

/* I2CRPT1 */
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CRPT1                            0x00000038
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CRPT1__DEFAULT                   0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CRPT1_STOP_SDAT2SDA__MASK        0x02      
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CRPT1_STOP_ENABLE__MASK          0x04      
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CRPT1_SCLT_DELAY__MASK           0x08      
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CRPT1_ENARPT_LEVEL__MASK         0x70      
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CRPT1_I2CT_ON__MASK              0x80      

/* I2CRPT2 */
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CRPT2                            0x00000039
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CRPT2__DEFAULT                   0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CRPT2_I2C_FASTMODE__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CRPT2_I2C_MEDIUMSPEED__MASK      0x02      

/* DACR1 */
#define RC8CODEW_C8CODEW_TOP_CTRL_DACR1                              0x00000040
#define RC8CODEW_C8CODEW_TOP_CTRL_DACR1__DEFAULT                     0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_DACR1_DAC_VALUE__MASK              0x0F      
#define FC8CODEW_C8CODEW_TOP_CTRL_DACR1_DAC_MODE__MASK               0xE0      

/* DACR2 */
#define RC8CODEW_C8CODEW_TOP_CTRL_DACR2                              0x00000041
#define RC8CODEW_C8CODEW_TOP_CTRL_DACR2__DEFAULT                     0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_DACR2_DAC_VALUE__MASK              0xFF      

/* SYS_IRQMSK */
#define RC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQMSK                         0x00000050
#define RC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQMSK__DEFAULT                0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQMSK_MDISEQC_IRQ_1__MASK     0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQMSK_MDISEQC_IRQ_2__MASK     0x02      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQMSK_MDISEQC_IRQ_3__MASK     0x04      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQMSK_MDISEQC_IRQ_4__MASK     0x08      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQMSK_MLNBCTRL_IRQ_1__MASK    0x10      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQMSK_MLNBCTRL_IRQ_2__MASK    0x20      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQMSK_MLNBCTRL_IRQ_3__MASK    0x40      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQMSK_MLNBCTRL_IRQ_4__MASK    0x80      

/* SYS_IRQSTATUS */
#define RC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQSTATUS                      0x00000051
#define RC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQSTATUS__DEFAULT             0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQSTATUS_SDISEQC_IRQ_1__MASK  0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQSTATUS_SDISEQC_IRQ_2__MASK  0x02      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQSTATUS_SDISEQC_IRQ_3__MASK  0x04      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQSTATUS_SDISEQC_IRQ_4__MASK  0x08      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQSTATUS_SLNBCTRL_IRQ_1__MASK 0x10      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQSTATUS_SLNBCTRL_IRQ_2__MASK 0x20      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQSTATUS_SLNBCTRL_IRQ_3__MASK 0x40      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQSTATUS_SLNBCTRL_IRQ_4__MASK 0x80      

/* SYS_IRQFORCE */
#define RC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQFORCE                       0x00000052
#define RC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQFORCE__DEFAULT              0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQFORCE_FDISEQC_IRQ_1__MASK   0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQFORCE_FDISEQC_IRQ_2__MASK   0x02      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQFORCE_FDISEQC_IRQ_3__MASK   0x04      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQFORCE_FDISEQC_IRQ_4__MASK   0x08      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQFORCE_FLNBCTRL_IRQ_1__MASK  0x10      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQFORCE_FLNBCTRL_IRQ_2__MASK  0x20      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQFORCE_FLNBCTRL_IRQ_3__MASK  0x40      
#define FC8CODEW_C8CODEW_TOP_CTRL_SYS_IRQFORCE_FLNBCTRL_IRQ_4__MASK  0x80      

/* TSRCSSEL */
#define RC8CODEW_C8CODEW_TOP_CTRL_TSRCSSEL                           0x0000007c
#define RC8CODEW_C8CODEW_TOP_CTRL_TSRCSSEL__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_TSRCSSEL_TSRCS_SEL__MASK           0x07      

/* AGCOBSSEL */
#define RC8CODEW_C8CODEW_TOP_CTRL_AGCOBSSEL                          0x0000007d
#define RC8CODEW_C8CODEW_TOP_CTRL_AGCOBSSEL__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_AGCOBSSEL_AGCOBS_SEL__MASK         0x03      

/* SDDATASEL */
#define RC8CODEW_C8CODEW_TOP_CTRL_SDDATASEL                          0x0000007e
#define RC8CODEW_C8CODEW_TOP_CTRL_SDDATASEL__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_SDDATASEL_SDDDATA1_SEL__MASK       0x07      
#define FC8CODEW_C8CODEW_TOP_CTRL_SDDATASEL_SDDDATA2_SEL__MASK       0x70      

/* SGNLGSEL */
#define RC8CODEW_C8CODEW_TOP_CTRL_SGNLGSEL                           0x0000007f
#define RC8CODEW_C8CODEW_TOP_CTRL_SGNLGSEL__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_SGNLGSEL_SGNLG1_SEL__MASK          0x07      
#define FC8CODEW_C8CODEW_TOP_CTRL_SGNLGSEL_SGNLG2_SEL__MASK          0x70      

/* GPIO0CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO0CFG                           0x00000080
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO0CFG__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO0CFG_GPIO0_XOR__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO0CFG_GPIO0_CONFIG__MASK        0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO0CFG_GPIO0_OPD__MASK           0x80      

/* GPIO1CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO1CFG                           0x00000081
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO1CFG__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO1CFG_GPIO1_XOR__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO1CFG_GPIO1_CONFIG__MASK        0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO1CFG_GPIO1_OPD__MASK           0x80      

/* GPIO2CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO2CFG                           0x00000082
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO2CFG__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO2CFG_GPIO2_XOR__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO2CFG_GPIO2_CONFIG__MASK        0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO2CFG_GPIO2_OPD__MASK           0x80      

/* GPIO3CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO3CFG                           0x00000083
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO3CFG__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO3CFG_GPIO3_XOR__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO3CFG_GPIO3_CONFIG__MASK        0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO3CFG_GPIO3_OPD__MASK           0x80      

/* GPIO4CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO4CFG                           0x00000084
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO4CFG__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO4CFG_GPIO4_XOR__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO4CFG_GPIO4_CONFIG__MASK        0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO4CFG_GPIO4_OPD__MASK           0x80      

/* GPIO5CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO5CFG                           0x00000085
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO5CFG__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO5CFG_GPIO5_XOR__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO5CFG_GPIO5_CONFIG__MASK        0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO5CFG_GPIO5_OPD__MASK           0x80      

/* GPIO6CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO6CFG                           0x00000086
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO6CFG__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO6CFG_GPIO6_XOR__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO6CFG_GPIO6_CONFIG__MASK        0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO6CFG_GPIO6_OPD__MASK           0x80      

/* GPIO7CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO7CFG                           0x00000087
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO7CFG__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO7CFG_GPIO7_XOR__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO7CFG_GPIO7_CONFIG__MASK        0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO7CFG_GPIO7_OPD__MASK           0x80      

/* GPIO8CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO8CFG                           0x00000088
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO8CFG__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO8CFG_GPIO8_XOR__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO8CFG_GPIO8_CONFIG__MASK        0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO8CFG_GPIO8_OPD__MASK           0x80      

/* GPIO9CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO9CFG                           0x00000089
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO9CFG__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO9CFG_GPIO9_XOR__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO9CFG_GPIO9_CONFIG__MASK        0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO9CFG_GPIO9_OPD__MASK           0x80      

/* GPIO10CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO10CFG                          0x0000008a
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO10CFG__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO10CFG_GPIO10_XOR__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO10CFG_GPIO10_CONFIG__MASK      0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO10CFG_GPIO10_OPD__MASK         0x80      

/* GPIO11CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO11CFG                          0x0000008b
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO11CFG__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO11CFG_GPIO11_XOR__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO11CFG_GPIO11_CONFIG__MASK      0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO11CFG_GPIO11_OPD__MASK         0x80      

/* GPIO12CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO12CFG                          0x0000008c
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO12CFG__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO12CFG_GPIO12_XOR__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO12CFG_GPIO12_CONFIG__MASK      0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO12CFG_GPIO12_OPD__MASK         0x80      

/* GPIO13CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO13CFG                          0x0000008d
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO13CFG__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO13CFG_GPIO13_XOR__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO13CFG_GPIO13_CONFIG__MASK      0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO13CFG_GPIO13_OPD__MASK         0x80      

/* GPIO14CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO14CFG                          0x0000008e
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO14CFG__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO14CFG_GPIO14_XOR__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO14CFG_GPIO14_CONFIG__MASK      0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO14CFG_GPIO14_OPD__MASK         0x80      

/* GPIO15CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO15CFG                          0x0000008f
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO15CFG__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO15CFG_GPIO15_XOR__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO15CFG_GPIO15_CONFIG__MASK      0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO15CFG_GPIO15_OPD__MASK         0x80      

/* GPIO16CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO16CFG                          0x00000090
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO16CFG__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO16CFG_GPIO16_XOR__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO16CFG_GPIO16_CONFIG__MASK      0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO16CFG_GPIO16_OPD__MASK         0x80      

/* GPIO17CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO17CFG                          0x00000091
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO17CFG__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO17CFG_GPIO17_XOR__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO17CFG_GPIO17_CONFIG__MASK      0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO17CFG_GPIO17_OPD__MASK         0x80      

/* GPIO18CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO18CFG                          0x00000092
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO18CFG__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO18CFG_GPIO18_XOR__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO18CFG_GPIO18_CONFIG__MASK      0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO18CFG_GPIO18_OPD__MASK         0x80      

/* GPIO19CFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO19CFG                          0x00000093
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIO19CFG__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO19CFG_GPIO19_XOR__MASK         0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO19CFG_GPIO19_CONFIG__MASK      0x7E      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIO19CFG_GPIO19_OPD__MASK         0x80      

/* GPIOOBS2 */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS2                           0x000000a1
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS2__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS2_GPIO_OBS16__MASK          0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS2_GPIO_OBS17__MASK          0x02      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS2_GPIO_OBS18__MASK          0x04      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS2_GPIO_OBS19__MASK          0x08      

/* GPIOOBS1 */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS1                           0x000000a2
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS1__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS1_GPIO_OBS8__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS1_GPIO_OBS9__MASK           0x02      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS1_GPIO_OBS10__MASK          0x04      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS1_GPIO_OBS11__MASK          0x08      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS1_GPIO_OBS12__MASK          0x10      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS1_GPIO_OBS13__MASK          0x20      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS1_GPIO_OBS14__MASK          0x40      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS1_GPIO_OBS15__MASK          0x80      

/* GPIOOBS0 */
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS0                           0x000000a3
#define RC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS0__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS0_GPIO_OBS0__MASK           0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS0_GPIO_OBS1__MASK           0x02      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS0_GPIO_OBS2__MASK           0x04      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS0_GPIO_OBS3__MASK           0x08      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS0_GPIO_OBS4__MASK           0x10      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS0_GPIO_OBS5__MASK           0x20      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS0_GPIO_OBS6__MASK           0x40      
#define FC8CODEW_C8CODEW_TOP_CTRL_GPIOOBS0_GPIO_OBS7__MASK           0x80      

/* TSTOUT */
#define RC8CODEW_C8CODEW_TOP_CTRL_TSTOUT                             0x000000f0
#define RC8CODEW_C8CODEW_TOP_CTRL_TSTOUT__DEFAULT                    0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_TSTOUT_TEST_OUT__MASK              0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_TSTOUT_TS__MASK                    0x1E      

/* TSTSYS */
#define RC8CODEW_C8CODEW_TOP_CTRL_TSTSYS                             0x000000f2
#define RC8CODEW_C8CODEW_TOP_CTRL_TSTSYS__DEFAULT                    0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_TSTSYS_DUPLMODE_OUT__MASK          0x01      
#define FC8CODEW_C8CODEW_TOP_CTRL_TSTSYS_TBUSDUPLOUT_MSK__MASK       0x06      

/* TBUSXXX2 */
#define RC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX2                           0x000000f4
#define RC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX2__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX2_TBUSXXX__MASK             0x03      
#define FC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX2_TS_INT__MASK              0x3C      
#define FC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX2_TB_TMGCOHER__MASK         0x80      

/* TBUSXXX1 */
#define RC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX1                           0x000000f5
#define RC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX1__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX1_TBUSXXX__MASK             0xFF      

/* TBUSXXX0 */
#define RC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX0                           0x000000f6
#define RC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX0__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_TBUSXXX0_TBUSXXX__MASK             0xFF      

/* BITSPEED1 */
#define RC8CODEW_C8CODEW_TOP_CTRL_BITSPEED1                          0x000000f7
#define RC8CODEW_C8CODEW_TOP_CTRL_BITSPEED1__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_BITSPEED1_BITSPEED__MASK           0xFF      

/* BITSPEED0 */
#define RC8CODEW_C8CODEW_TOP_CTRL_BITSPEED0                          0x000000f8
#define RC8CODEW_C8CODEW_TOP_CTRL_BITSPEED0__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_BITSPEED0_BITSPEED__MASK           0xFF      

/* TBUSBIT1 */
#define RC8CODEW_C8CODEW_TOP_CTRL_TBUSBIT1                           0x000000f9
#define RC8CODEW_C8CODEW_TOP_CTRL_TBUSBIT1__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_TBUSBIT1_TBUSBIT1_SELECT__MASK     0x7F      
#define FC8CODEW_C8CODEW_TOP_CTRL_TBUSBIT1_OUT_BIT1__MASK            0x80      

/* TBUSBIT2 */
#define RC8CODEW_C8CODEW_TOP_CTRL_TBUSBIT2                           0x000000fa
#define RC8CODEW_C8CODEW_TOP_CTRL_TBUSBIT2__DEFAULT                  0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_TBUSBIT2_TBUSBIT2_SELECT__MASK     0x7F      
#define FC8CODEW_C8CODEW_TOP_CTRL_TBUSBIT2_OUT_BIT2__MASK            0x80      

/* I2CMAPOCFG */
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CMAPOCFG                         0x000000fb
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CMAPOCFG__DEFAULT                0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CMAPOCFG_I2CBIT_OBS2__MASK       0x07      
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CMAPOCFG_I2CMAPO2M_ON__MASK      0x08      
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CMAPOCFG_I2CBIT_OBS1__MASK       0x70      
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CMAPOCFG_I2CMAPO1M_ON__MASK      0x80      

/* I2CMAPO11 */
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO11                          0x000000fc
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO11__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO11_I2CMAP_OBS1__MASK        0x7F      

/* I2CMAPO10 */
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO10                          0x000000fd
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO10__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO10_I2CMAP_OBS1__MASK        0xFF      

/* I2CMAPO21 */
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO21                          0x000000fe
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO21__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO21_I2CMAP_OBS2__MASK        0x7F      

/* I2CMAPO20 */
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO20                          0x000000ff
#define RC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO20__DEFAULT                 0x0       
#define FC8CODEW_C8CODEW_TOP_CTRL_I2CMAPO20_I2CMAP_OBS2__MASK        0xFF      


/* Number of registers */
#define C8CODEW_C8CODEW_TOP_CTRL_REG_NBREGS                          59        

/* Number of fields */
#define C8CODEW_C8CODEW_TOP_CTRL_REG_NBFIELDS                        172       



#endif /* #ifndef _C8CODEW_TOP_CTRL_REG_INIT_H */
