/* 
* This file is part of STiD135 OXFORD LLA 
* 
* Copyright (c) <2014>-<2018>, STMicroelectronics - All Rights Reserved 
* Author(s): Mathias Hilaire (mathias.hilaire@st.com), Thierry Delahaye (thierry.delahaye@st.com) for STMicroelectronics. 
* 
* License terms: BSD 3-clause "New" or "Revised" License. 
* 
* Redistribution and use in source and binary forms, with or without 
* modification, are permitted provided that the following conditions are met: 
* 
* 1. Redistributions of source code must retain the above copyright notice, this 
* list of conditions and the following disclaimer. 
* 
* 2. Redistributions in binary form must reproduce the above copyright notice, 
* this list of conditions and the following disclaimer in the documentation 
* and/or other materials provided with the distribution. 
* 
* 3. Neither the name of the copyright holder nor the names of its contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
* 
*/ 
#ifndef _DVBSX_DISEQC_REG_INIT_H
#define _DVBSX_DISEQC_REG_INIT_H

/* -------------------------------------------------------------------------
 * File name  : dvbsx_diseqc_reg_init.h
 * File type  : C header file
 * -------------------------------------------------------------------------
 * Description:  Register map constants
 * Generated by spirit2regtest v2.24_alpha3
 * -------------------------------------------------------------------------
 */


/* Register map constants */

/* DISIRQCFG */
#define RC8CODEW_DVBSX_DISEQC_DISIRQCFG                              0x00000000
#define RC8CODEW_DVBSX_DISEQC_DISIRQCFG__DEFAULT                     0x0       
#define FC8CODEW_DVBSX_DISEQC_DISIRQCFG_ENGAPBURST__MASK             0x01      
#define FC8CODEW_DVBSX_DISEQC_DISIRQCFG_ENTXFIFO64B__MASK            0x02      
#define FC8CODEW_DVBSX_DISEQC_DISIRQCFG_ENTXEND__MASK                0x04      
#define FC8CODEW_DVBSX_DISEQC_DISIRQCFG_ENTIMEOUT__MASK              0x08      
#define FC8CODEW_DVBSX_DISEQC_DISIRQCFG_ENTRFINISH__MASK             0x10      
#define FC8CODEW_DVBSX_DISEQC_DISIRQCFG_ENRXFIFO8B__MASK             0x20      
#define FC8CODEW_DVBSX_DISEQC_DISIRQCFG_ENRXEND__MASK                0x40      

/* DISIRQSTAT */
#define RC8CODEW_DVBSX_DISEQC_DISIRQSTAT                             0x00000001
#define RC8CODEW_DVBSX_DISEQC_DISIRQSTAT__DEFAULT                    0x0       
#define FC8CODEW_DVBSX_DISEQC_DISIRQSTAT_IRQGAPBURST__MASK           0x01      
#define FC8CODEW_DVBSX_DISEQC_DISIRQSTAT_IRQTXFIFO64B__MASK          0x02      
#define FC8CODEW_DVBSX_DISEQC_DISIRQSTAT_IRQTXEND__MASK              0x04      
#define FC8CODEW_DVBSX_DISEQC_DISIRQSTAT_IRQTIMEOUT__MASK            0x08      
#define FC8CODEW_DVBSX_DISEQC_DISIRQSTAT_IRQTRFINISH__MASK           0x10      
#define FC8CODEW_DVBSX_DISEQC_DISIRQSTAT_IRQRXFIFO8B__MASK           0x20      
#define FC8CODEW_DVBSX_DISEQC_DISIRQSTAT_IRQRXEND__MASK              0x40      

/* DISTXCFG */
#define RC8CODEW_DVBSX_DISEQC_DISTXCFG                               0x00000002
#define RC8CODEW_DVBSX_DISEQC_DISTXCFG__DEFAULT                      0x0       
#define FC8CODEW_DVBSX_DISEQC_DISTXCFG_DISEQC_MODE__MASK             0x03      
#define FC8CODEW_DVBSX_DISEQC_DISTXCFG_DIS_PRECHARGE__MASK           0x04      
#define FC8CODEW_DVBSX_DISEQC_DISTXCFG_ENVELOP__MASK                 0x08      
#define FC8CODEW_DVBSX_DISEQC_DISTXCFG_TIM_CMD__MASK                 0x30      
#define FC8CODEW_DVBSX_DISEQC_DISTXCFG_TIM_OFF__MASK                 0x40      
#define FC8CODEW_DVBSX_DISEQC_DISTXCFG_DISTX_RESET__MASK             0x80      

/* DISTXSTATUS */
#define RC8CODEW_DVBSX_DISEQC_DISTXSTATUS                            0x00000003
#define RC8CODEW_DVBSX_DISEQC_DISTXSTATUS__DEFAULT                   0x0       
#define FC8CODEW_DVBSX_DISEQC_DISTXSTATUS_TR_FINISH__MASK            0x01      
#define FC8CODEW_DVBSX_DISEQC_DISTXSTATUS_TR_TIMEOUT__MASK           0x02      
#define FC8CODEW_DVBSX_DISEQC_DISTXSTATUS_TX_END__MASK               0x04      
#define FC8CODEW_DVBSX_DISEQC_DISTXSTATUS_TX_FIFO64B__MASK           0x08      
#define FC8CODEW_DVBSX_DISEQC_DISTXSTATUS_GAP_BURST__MASK            0x10      
#define FC8CODEW_DVBSX_DISEQC_DISTXSTATUS_TX_IDLE__MASK              0x20      
#define FC8CODEW_DVBSX_DISEQC_DISTXSTATUS_TX_FIFO_FULL__MASK         0x40      

/* DISTXBYTES */
#define RC8CODEW_DVBSX_DISEQC_DISTXBYTES                             0x00000004
#define RC8CODEW_DVBSX_DISEQC_DISTXBYTES__DEFAULT                    0x0       
#define FC8CODEW_DVBSX_DISEQC_DISTXBYTES_TXFIFO_BYTES__MASK          0xFF      

/* DISTXFIFO */
#define RC8CODEW_DVBSX_DISEQC_DISTXFIFO                              0x00000005
#define RC8CODEW_DVBSX_DISEQC_DISTXFIFO__DEFAULT                     0x0       
#define FC8CODEW_DVBSX_DISEQC_DISTXFIFO_DISEQC_TX_FIFO__MASK         0xFF      

/* DISTXF22 */
#define RC8CODEW_DVBSX_DISEQC_DISTXF22                               0x00000006
#define RC8CODEW_DVBSX_DISEQC_DISTXF22__DEFAULT                      0x0       
#define FC8CODEW_DVBSX_DISEQC_DISTXF22_F22TX__MASK                   0xFF      

/* DISTXWAIT */
#define RC8CODEW_DVBSX_DISEQC_DISTXWAIT                              0x00000007
#define RC8CODEW_DVBSX_DISEQC_DISTXWAIT__DEFAULT                     0x0       
#define FC8CODEW_DVBSX_DISEQC_DISTXWAIT_DISTXWAIT_VAL__MASK          0xFF      

/* DISTIMEOCFG */
#define RC8CODEW_DVBSX_DISEQC_DISTIMEOCFG                            0x00000008
#define RC8CODEW_DVBSX_DISEQC_DISTIMEOCFG__DEFAULT                   0x0       
#define FC8CODEW_DVBSX_DISEQC_DISTIMEOCFG_TIMEOUT_OFF__MASK          0x01      
#define FC8CODEW_DVBSX_DISEQC_DISTIMEOCFG_RXCHOICE__MASK             0x06      
#define FC8CODEW_DVBSX_DISEQC_DISTIMEOCFG_ONECHIP_TRX__MASK          0x80      

/* DISTIMEOUT */
#define RC8CODEW_DVBSX_DISEQC_DISTIMEOUT                             0x00000009
#define RC8CODEW_DVBSX_DISEQC_DISTIMEOUT__DEFAULT                    0x0       
#define FC8CODEW_DVBSX_DISEQC_DISTIMEOUT_TIMEOUT_COUNT__MASK         0xFF      

/* DISRXCFG */
#define RC8CODEW_DVBSX_DISEQC_DISRXCFG                               0x0000000a
#define RC8CODEW_DVBSX_DISEQC_DISRXCFG__DEFAULT                      0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXCFG_DISRX_ON__MASK                0x01      
#define FC8CODEW_DVBSX_DISEQC_DISRXCFG_SIGNED_RXIN__MASK             0x02      
#define FC8CODEW_DVBSX_DISEQC_DISRXCFG_IGNORE_SHORT22K__MASK         0x04      
#define FC8CODEW_DVBSX_DISEQC_DISRXCFG_PINSELECT__MASK               0x38      
#define FC8CODEW_DVBSX_DISEQC_DISRXCFG_EXTENVELOP__MASK              0x40      
#define FC8CODEW_DVBSX_DISEQC_DISRXCFG_DISRX_RESET__MASK             0x80      

/* DISRXSTAT1 */
#define RC8CODEW_DVBSX_DISEQC_DISRXSTAT1                             0x0000000b
#define RC8CODEW_DVBSX_DISEQC_DISRXSTAT1__DEFAULT                    0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT1_FIFOEMPTY__MASK             0x04      
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT1_8BFIFOREADY__MASK           0x08      
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT1_CONTTONE__MASK              0x10      
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT1_RXDETECT__MASK              0x20      
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT1_RXACTIVE__MASK              0x40      
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT1_RXEND__MASK                 0x80      

/* DISRXSTAT0 */
#define RC8CODEW_DVBSX_DISEQC_DISRXSTAT0                             0x0000000c
#define RC8CODEW_DVBSX_DISEQC_DISRXSTAT0__DEFAULT                    0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT0_RXMSGLOST__MASK             0x04      
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT0_SHORT22K__MASK              0x08      
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT0_FIFOOVF__MASK               0x10      
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT0_RXNONBYTE__MASK             0x20      
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT0_FIFOPFAIL__MASK             0x40      
#define FC8CODEW_DVBSX_DISEQC_DISRXSTAT0_RXFAIL__MASK                0x80      

/* DISRXBYTES */
#define RC8CODEW_DVBSX_DISEQC_DISRXBYTES                             0x0000000d
#define RC8CODEW_DVBSX_DISEQC_DISRXBYTES__DEFAULT                    0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXBYTES_RXFIFO_BYTES__MASK          0x1F      

/* DISRXPARITY1 */
#define RC8CODEW_DVBSX_DISEQC_DISRXPARITY1                           0x0000000e
#define RC8CODEW_DVBSX_DISEQC_DISRXPARITY1__DEFAULT                  0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXPARITY1_DISRX_PARITY__MASK        0xFF      

/* DISRXPARITY0 */
#define RC8CODEW_DVBSX_DISEQC_DISRXPARITY0                           0x0000000f
#define RC8CODEW_DVBSX_DISEQC_DISRXPARITY0__DEFAULT                  0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXPARITY0_DISRX_PARITY__MASK        0xFF      

/* DISRXFIFO */
#define RC8CODEW_DVBSX_DISEQC_DISRXFIFO                              0x00000010
#define RC8CODEW_DVBSX_DISEQC_DISRXFIFO__DEFAULT                     0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXFIFO_DISEQC_RX_FIFO__MASK         0xFF      

/* DISRXDC1 */
#define RC8CODEW_DVBSX_DISEQC_DISRXDC1                               0x00000011
#define RC8CODEW_DVBSX_DISEQC_DISRXDC1__DEFAULT                      0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXDC1_DC_VALUE__MASK                0x03      

/* DISRXDC0 */
#define RC8CODEW_DVBSX_DISEQC_DISRXDC0                               0x00000012
#define RC8CODEW_DVBSX_DISEQC_DISRXDC0__DEFAULT                      0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXDC0_DC_VALUE__MASK                0xFF      

/* DISRXKOFF */
#define RC8CODEW_DVBSX_DISEQC_DISRXKOFF                              0x00000013
#define RC8CODEW_DVBSX_DISEQC_DISRXKOFF__DEFAULT                     0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXKOFF_K_OFFSET_EXP__MASK           0x0F      
#define FC8CODEW_DVBSX_DISEQC_DISRXKOFF_K_OFFSET_MAN__MASK           0xE0      

/* DISRXF221 */
#define RC8CODEW_DVBSX_DISEQC_DISRXF221                              0x00000014
#define RC8CODEW_DVBSX_DISEQC_DISRXF221__DEFAULT                     0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXF221_F22RX__MASK                  0x0F      

/* DISRXF220 */
#define RC8CODEW_DVBSX_DISEQC_DISRXF220                              0x00000015
#define RC8CODEW_DVBSX_DISEQC_DISRXF220__DEFAULT                     0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXF220_F22RX__MASK                  0xFF      

/* DISRXF100 */
#define RC8CODEW_DVBSX_DISEQC_DISRXF100                              0x00000016
#define RC8CODEW_DVBSX_DISEQC_DISRXF100__DEFAULT                     0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXF100_F100RX__MASK                 0xFF      

/* DISRXK1 */
#define RC8CODEW_DVBSX_DISEQC_DISRXK1                                0x00000017
#define RC8CODEW_DVBSX_DISEQC_DISRXK1__DEFAULT                       0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXK1_K1_OFFSET_EXP__MASK            0x07      
#define FC8CODEW_DVBSX_DISEQC_DISRXK1_K1K2_FACTOR2X__MASK            0x08      
#define FC8CODEW_DVBSX_DISEQC_DISRXK1_K1_OFFSET_MAN__MASK            0xF0      

/* DISRXK2 */
#define RC8CODEW_DVBSX_DISEQC_DISRXK2                                0x00000018
#define RC8CODEW_DVBSX_DISEQC_DISRXK2__DEFAULT                       0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXK2_K2_OFFSET_EXP__MASK            0x0F      
#define FC8CODEW_DVBSX_DISEQC_DISRXK2_K2_OFFSET_MAN__MASK            0xF0      

/* DISRXPK */
#define RC8CODEW_DVBSX_DISEQC_DISRXPK                                0x00000019
#define RC8CODEW_DVBSX_DISEQC_DISRXPK__DEFAULT                       0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXPK_APK__MASK                      0x0F      
#define FC8CODEW_DVBSX_DISEQC_DISRXPK_BPK__MASK                      0xF0      

/* DISRXENV */
#define RC8CODEW_DVBSX_DISEQC_DISRXENV                               0x0000001a
#define RC8CODEW_DVBSX_DISEQC_DISRXENV__DEFAULT                      0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXENV_ATH__MASK                     0x0F      
#define FC8CODEW_DVBSX_DISEQC_DISRXENV_K_ENV__MASK                   0xE0      

/* DISRXVMIN */
#define RC8CODEW_DVBSX_DISEQC_DISRXVMIN                              0x0000001b
#define RC8CODEW_DVBSX_DISEQC_DISRXVMIN__DEFAULT                     0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXVMIN_VMIN__MASK                   0xFF      

/* DISRXSHORT22K */
#define RC8CODEW_DVBSX_DISEQC_DISRXSHORT22K                          0x0000001c
#define RC8CODEW_DVBSX_DISEQC_DISRXSHORT22K__DEFAULT                 0x0       
#define FC8CODEW_DVBSX_DISEQC_DISRXSHORT22K_SHORT22K_LENGTH__MASK    0x1F      

/* ACRPRESC */
#define RC8CODEW_DVBSX_DISEQC_ACRPRESC                               0x0000001e
#define RC8CODEW_DVBSX_DISEQC_ACRPRESC__DEFAULT                      0x0       
#define FC8CODEW_DVBSX_DISEQC_ACRPRESC_ACR_PRESC__MASK               0x07      
#define FC8CODEW_DVBSX_DISEQC_ACRPRESC_ACR_CODFRDY__MASK             0x08      

/* ACRDIV */
#define RC8CODEW_DVBSX_DISEQC_ACRDIV                                 0x0000001f
#define RC8CODEW_DVBSX_DISEQC_ACRDIV__DEFAULT                        0x0       
#define FC8CODEW_DVBSX_DISEQC_ACRDIV_ACR_DIV__MASK                   0xFF      


/* Number of registers */
#define C8CODEW_DVBSX_DISEQC_REG_NBREGS                              31        

/* Number of fields */
#define C8CODEW_DVBSX_DISEQC_REG_NBFIELDS                            78        



#endif /* #ifndef _DVBSX_DISEQC_REG_INIT_H */
